Next generation memory such as Double Data Rate (DDR) technologies (e.g. LP4x, DDR5, LP5, etc.) have been purposed for lower area and lower power. Current DDRx (where, ‘x’ is a number) matched receiver (RX) architecture is analog intensive with circuits that rely on bias currents, which are difficult for power management. Also, this RX architecture does not scale well, as it is power and area hungry.